Typical prior art SAs (Sense Amplifiers) used in conjunction with SRAM (Static Random Access Memory) provide only dynamic output signals. Thus the output needs to be captured within the period of the read cycle by a read-out latch. When operating in conjunction with a high frequency pipeline SRAM, such a dynamic output signal is hard to catch and distribute. Further, transmission delay concerns require that the SA be physically close to the read-out latch in these prior art circuits. When applicable, multiple SA outputs may be collected by a dynamic dotted OR circuit. Such a dotted OR circuit consumes relatively large amounts of power, especially when operating in the dynamic mode, and further occupies a large amount of space on an integrated circuit chip. The alternative to the use of a dotted OR circuit, when collecting multiple SA outputs, is to multiplex the SA outputs to a load.
It would thus be desirable to be able to design a multiple SA read-out path that has relatively low power consumption and does not require that the SA be physically close to the read-out latch.